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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 313 - Computer Organization Lecture 23 - Course Review December 5, 2003

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ECE 313 Fall 2003Lecture 23 - Review2 Solution - Exercise 6.1 Clock cycle time for single cycle implementation: 10ns (was 8ns) Single-cycle completes 1 instruction / cycle 10ns / instruction Clock cycle for time pipelined implementation: 4ns (was 2ns) Pipelined implementation completes 1 instruction / cycle 4ns / instruction Speedup = 10ns / 4ns = 2.5

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ECE 313 Fall 2003Lecture 23 - Review3 Solution - Exercise 6.2 Forward to lower input of EX

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ECE 313 Fall 2003Lecture 23 - Review4 Solution - Exercise 6.4 Dependencies add $2, $5, $4 add $4, $2, $5 sw $5, 100($2) add $3, $2, $4 All dependencies can be resolved via forwarding Reminder: load-use can’t be resolved with forwarding (stall required): lw $6, $8, $9 add $10, $6, $7

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ECE 313 Fall 2003Lecture 23 - Review5 Solution - Exercise 6.8

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ECE 313 Fall 2003Lecture 23 - Review6 Solution - Exercise 7.7 1 4 8 5 20 17 19 Hit / Miss 56 9 11 4 43 5 6 9 Ref. 17 0 1 2 3 4 5 6 Address in Cache 7 8 9 10 11 12 13 14 Block 15 MISS 1 4 8 5 20 MISS 17 MISS 19 MISS 56MISS 9 11 MISS 4 43 HIT MISS 6 HIT References Cache Contents

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ECE 313 Fall 2003Lecture 23 - Review7 Solution - Exercise 7.9 Each block contains: 4 32-bit words 1 16-bit tag 1 Valid bit Times 4096 blocks 593,920 bits 74,240 bytes

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ECE 313 Fall 2003Lecture 23 - Review8 Solution - Exercise 7.15 Average Memory Access Time = Hit Time + Miss Rate X Miss Penalty Information Given: 2ns clock period 1 cycle access time on hit 20 cycle access time on miss Miss rate: 0.05 misses per instruction Solution: AMAT = 2ns + 0.05 X 40ns = 4ns

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ECE 313 Fall 2003Lecture 23 - Review9 Roadmap for the term: major topics Overview / Abstractions and Technology Performance Instruction sets Logic & arithmetic Processor Implementation Single-cycle implemenatation Multicycle implementation Pipelined Implementation Memory systems Input/Output

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ECE 313 Fall 2003Lecture 23 - Review10 Course Review: Important Topics Chapter 1 - Computer Abstractions and Technology The 5 basic components of a computer system Technology Trends Chapter 2: Performance Defining performance as execution time Basic Metrics Execution time Number of instructions / program Number of cycles / program Cycles / instruction The performance equation and simple calculations

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ECE 313 Fall 2003Lecture 23 - Review11 Course Review: Important Topics (cont'd) Chapter 3 - Instruction Sets Principles of Instruction Set Design Details of MIPS Instruction Set Instruction Formats (R-Type, I-Type, J-Type) Specific Instructions Chapter 4: Logic & Arithmetic Number Representations Adder Design: Basic design, carry lookahead, subtraction Logical Operations ALU Design Multiplication & Division Floating Point

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ECE 313 Fall 2003Lecture 23 - Review12 Course Review: Important Topics (cont'd) Chapter 5 - Basic Processor Design Single-Cycle Processor Implementation Multi-Cycle Processor Implementation Basic Implementation Microprogramming Chapter 6: Pipelined Design Pipelined Datatpath Pipelined Control Forwarding Hazards and Stalls

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ECE 313 Fall 2003Lecture 23 - Review13 Course Review: Important Topics (cont'd) Chapter 7: Memory Systems Memory Technology Caches Virtual Memory Chapter 8: Input / Output I/O Devices and characteristics Disk Characteristics Buses Interfacing Verilog Combinational, sequential, and structural circuits

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ECE 313 Fall 2003Lecture 23 - Review14 Possible Exam Problems... Design Problems - add instruction or feature to... Multicycle Processor Design Pipelined Processor Design Intermediate Problems Performance MIPS Assembly / Machine Language Arithmetic / Logic / ALU Design ; Floating Point Pipelining Memory systems / caches Verilog Short Answer ("concept") problems - all topics

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